1. Field of the Invention
The invention relates to a circuit board and the method for manufacturing the same and more particularly, to a circuit board with a buried conductive trace formed thereon and the method for manufacturing the same.
2. Description of the Related Art
Recently, as electronic devices have become multifunctional, technology for package substrates has been rapidly developed so as to realize lightweight, thin short, small, and highly integrated fine circuit patterns. In particular, such lightweight, thin, short, small, and highly integrated fine circuit patterns are required for the Chip Scale Package (CSP) product group. In order to form fine circuit patterns on a small substrate, a press method is typically used to form a buried conductive trace on the substrate.
Referring to FIGS. 1a to 1h, a conventional method for forming a buried conductive trace on a substrate is first to form a copper layer 120 on a carrier 110. The copper layer 120 has protrusion structures 122, 124 and the pattern of the protrusion structures 122, 124 is corresponding to that of the conductive trace desired to be formed on a substrate (see FIGS. 1a and 1b). Afterward, the carrier 110 is pressed to a soft substrate 130, such as a B-stage Bismaleimide Triazine (BT) substrate such that the protrusion structures 122, 124 of the copper layer 120 are buried on a surface 132 of the substrate 130. A surface 134 opposite to the surface 132 of the substrate 130 can be optionally pressed with another copper layer 140 having protrusion structures 142 so as to form a conductive trace on the surface 134 (see FIG. 1c). The carriers 110 are separated from the copper layers 120, 140 and the copper layers 120, 140 are then thinned by etching so that the surfaces 132, 134 of the substrate 130 are exposed and the structures 122, 124, 142 still remain on and are flush with the surfaces 132, 134 of the substrate 130, respectively. The buried structures 122, 124, 142 will finally form the conductive trace layers on the substrate 130 (see FIG. 1d).
Subsequently, through holes 150 are formed on the substrate 130 by etching or drilling and a copper layer 160 is formed on the surfaces 132, 134 of the substrate 130 and on the inner walls of the through holes 150 by electroless plating (see FIG. 1e). A layer of dry film 170 is then formed on the surfaces 132, 134 of the substrate 130 to act as a plating mask in such a manner that the conductive trace layers on the substrate 130, i.e. the buried structures 122, 124, 142 are covered with the dry film 170 and the through holes 150 are exposed from the dry film 170. Next, the inner walls of the through holes 150 are plated with a copper layer 180 (see FIG. 1f). Afterward, the dry film 170 and the copper layer 160 formed on the surfaces 132, 134 of the substrate 130 by electroless plating are removed. Subsequently, a solder mask 190 is formed on the surfaces 132, 134 of the substrate 130 and exposes the structures 122, 124 and 142. The exposed portions of the structures 122, 124 and 142 are applied with a layer of organic solderability preservative (OSP) (see FIG. 1g). Next, the dry film 170 is formed on the structures 122 and 142 again and the structure 124 is plated with a nickel/gold layer 195 (see FIG. 1h). Finally, the dry film 170 is removed from the substrate 130.
The above structures 124 plated with the Ni/Au layer 195 are to be used as fingers to electrically connect to external circuitry through bonding wires. The structures 122 and 142 are to be used as pads to electrically connect to external circuitry through solder balls. Since the finger structures 124 are required to be plated with the Ni/Au layer 195, all the structures 124 are electrically connected together to facilitate the implementation of plating. However, the electrical performance of the structures 124 cannot be tested after being plated since they are electrically connected together.
Moreover, the resulting pad structures 122 are flush with the surface 132 of the substrate 130 and the solder mask 190 usually has a non-negligible thickness. Therefore, when the pad structures 122 are electrically connected to a chip by solder balls, the solder balls will have only a small portion of the thickness protruding from the solder mask 190 (not shown in the figure). As a result, this will lead to a small die gap between the chip and substrate 130. When an underfill material or molding compound is used to protect the chip in a subsequent package process, it is not easy to fill up the die gap with them. Thus, voids will be formed in the underfill material or molding compound in the die gap.
Accordingly, there exists a need to provide a method for manufacturing a circuit board with a buried conductive trace formed thereon to solve the above-mentioned problems.